1. Field of the Invention
The present invention relates to fabrication of transistors in integrated circuit devices. Specifically, the present invention provides an improved method for fabricating an integrated circuit device including N-channel and P-channel transistors having selectively hardened gate oxides.
2. State of the Art
State of the art integrated circuit (IC) devices generally require transistors including hardened gate oxides. As feature dimensions continually decrease, gate oxides are hardened in order to prevent diffusion of dopants from overlying layers into and through the gate oxide, to prevent breakdown at voltages below normal operating parameters, and to confer resistance to hot electron degradation. State of the art transistors including hardened gate oxides, therefore, often possess performance and reliability advantages relative to transistors including non-hardened gate oxides applied in the same context. However, hardened gate oxides are not desirable in all IC applications, and known methods for hardening gate oxides often require significant design and performance tradeoffs.
While it is generally preferred to harden the gate oxides of P-channel devices due to the nature of P-type dopants, such is not the case for N-channel devices. Hardening of N-channel devices is generally not necessary as N-type dopants do not readily diffuse through non-hardened gate oxides. Moreover, hardening N-channel devices is often undesirable due to compounding performance problems. As is well known, hardening of gate oxides included in N-channel devices leads to significant threshold voltage (VT) roll-off. While VT roll-off can be counteracted through enhancement implants, the increased dopant concentration resulting from enhancement implants causes additional performance problems, such as refresh degradation and reduced surface mobility. Therefore, it would generally be advantageous not to harden the gate oxides of N-channel devices included within an IC device.
Despite the difficulties generally resulting from hardening the gate oxides of N-channel devices, however, the ability to selectively harden the gate oxides of N-channel devices in particular instances would be advantageous.
Additionally, as is also well known, it is often desirable to include P-channel or N-channel devices having gate oxides of varying thicknesses within a single IC device. For instance, it is beneficial to provide N-channel devices with gate oxides which are thicker than the thin, hardened gate oxides generally included in P-channel devices. Increasing the thickness of non-hardened N-channel gate oxides increases the VT of the corresponding N-channel devices, thereby decreasing control and performance the same. Moreover, it may also be advantageous to fabricate an IC device including hardened P-channel or N-channel devices incorporating hardened gate oxides of varying thicknesses.
Therefore, an ideal method for fabricating IC devices would facilitate simple and low-cost fabrication of IC devices including P-channel and N-channel devices which have been selectively hardened and which may include hardened or non-hardened gate oxides of varying thicknesses. However, known methods for hardening gate oxides generally do not provide the flexibility needed to enable selective hardening of gate oxides within an IC device. Furthermore, though it is possible to fabricate hardened gate oxides of varying thicknesses using known techniques, such techniques generally require additional etch steps, which are costly and serve as an additional source of error in a fabrication process.
For example, known methods for hardening gate oxides included in an IC device, such as a dynamic random access memory (DRAM) device, often require blanket hardening of a gate oxide layer deposited over a semiconductor substrate. During subsequent fabrication steps, both N-channel and P-channel gate oxides must then be formed using the blanket hardened gate oxide layer. Consequently, every one of the N-channel and P-Channel devices included in the subsequently formed IC device includes a hardened gate oxide. Blanket hardening processes simply do not enable selective hardening of particular areas of the gate oxide layer and, thereby, compromise the quality of IC devices fabricated by such methods.
Additionally, blanket hardening techniques cause difficultly in fabricating IC devices including gate oxides of varying thicknesses. Hardened oxide layers generally will not grow significantly during subsequent thermal oxidation processes. Therefore, to fabricate an IC device having gate oxides of various thicknesses using a blanket hardening process, the gate oxide layer must be formed such that, after hardening, the hardened gate oxide layer is as thick as the thickest desired gate oxide. The hardened gate oxide layer must then be selectively etched back to a desired thickness where P-channel or N-channel devices having thinner gate oxides are to be formed. Such a process is disadvantageous because it adds the cost and complication associated with one, or more additional etch steps. Moreover, known etching processes are difficult to control where only minute amounts of material must be removed. Thus, as the thickness of state of the art gate oxides shrinks well below 70 Angstroms, the need to etch back a hardened gate oxide layer becomes increasingly problematic and can only serve as a source of error, decreasing fabrication throughput as well as device reliability.
As can be appreciated, an improved method for fabricating IC devices including selectively hardening gate oxides is needed. Such an improved method should not only enable fabrication of P-channel and N-channel devices including selectively hardened gate oxides but also enable fabrication of such devices including hardened or non-hardened gate oxides of varying thicknesses without requiring additional etch steps.